Sangline Thomas

About Sangline Thomas

Worked on almost every phase of ASIC/FPGA design. Well versed with all the leading ASIC and FPGA design, verification, debug and Validation tools. Expertise in VHDL and Verilog languages.Was part of multiple system design projects. Very strong FPGA design, verification and debug skills. SpecialtiesFPGA DesignVerilog, VHDLSystem VerilogMentor design tools ( Modelsim, Questasim )Xilinx design tools ( ISE, PLANAHED, EDK, CHIPSCOPE )I was working on VHDL HDL & Verilog HDL for FPGA Design.Functional simulation and timing simulation with Modelsim/Questasim/ ISE tool.RTL DesignFSM based design UART ProtocolSynthesisMatlab and System Generator

Experience

1. Sr Lead Engineer

   Qualcomm

   Jun 2019 — Present · Bengaluru, IN

Education

• Dr. Paul's Engineering College

  Bachelor's Degree, Electronics and Communication

  2009 — 2012

• Technical High School, Cheruvathur

  High School, Electronics

  2003 — 2006

• Anna University Chennai

  Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering

• Model Poly Technic College, Kalliassery

  Engineer's Degree, Medical Electronics

  2006 — 2009

Skills

• Field-Programmable Gate Arrays (Fpga)
• Questasim
• Microcontrollers
• Xilinx
• Ise
• Vlsi
• Matlab
• Logic Synthesis
• Fpga Prototyping
• Hardware
• Assertion Based Verification
• Functional Verification
• Fsm Based Design
• Modelsim
• Vhdl
• Simulations
• Verilog
• Rtl Design
• Gsm
• Systems Design
• Uart
• Synthesis
• Debugging
• Microchip Pic
• Fpga
• Digital Electronics
• Very-Large-Scale Integration (Vlsi)