Sandip Bhadani

About Sandip Bhadani

11 years of experience in ASIC verification including the development of Verification IPs, Test Plan definition and test case development, development of verification environment & SoC Verification.• Experience in System Verilog Based Verification IP development, BFM development, and functional coverage. • Experience of working as a team member for I2C VIP, AMBA AHB VIP and AMBA AXI VIP, SPI VIP, MIPI DSI VIP development using OVM, UVM and Pure System Verilog environment.• Experience in working on LP DDR4 memory controller\'s monitor and verification test-plan development. • Experience in working with camera SoC and subsystem verification. • Experience in verification of PCIE phy. • Experience in working with FPGA Full Chip Verification.

Experience

1. Ic Design Verification Engineer Iv

   Broadcom

   Aug 2021 — Present · Bengaluru, IN

Education

• Dharmsinh Desai University

  Bacholar of Engineering, Electronics

  2008 — 2012

• Saint xavier higher secondary school

  High school teaching, science

  2006 — 2008

Skills

• Cadence
• Soc
• Very-Large-Scale Integration (Vlsi)
• Rtl Verification
• Systemverilog
• Vlsi
• Static Timing Analysis
• Amba Axi
• Pcie
• Asic
• Uvm
• Universal Verification Methodology (Uvm)
• Verilog
• Amba Ahb
• Axi
• Embedded Systems
• System on a Chip (Soc)
• Open Verification Methodology
• Application-Specific Integrated Circuits (Asic)
• I2c