Sandesh Pandey
Design Verification Engineer at Synopsys || Ex Qualcomm || BITS Pilani
- Role
- Staff Engineer at 新思科技股份有限公司
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sandesh Pandey
7 year Experienced in Verification IP development in UVM environment. Skilled in Verilog, System Verilog,UVM and C. Strong engineering professional with a Master’s of Technology focused in microelectronics Engineering from BITS Pilani.
Experience
Staff Engineer
Jun 2024 — Present · Bengaluru, IN
Education
Birla Institute of Technology and Science, Pilani
Master of Technology - MTech, Microelectronics
Dr. A.P.J. Abdul Kalam Technical University
Bachelor's of Technology , Electronics & Communication Engineering
2013 — 2017
jwala devi SVM allahabad UP India
Intermediate(12th), basice education
2011 — 2012
Jwala devi SVM Allahabad UP India
High School (10th ), Basic Education
2010 — 2010
Skills
- Leadership
- Verilog
- Engineering
- Universal Verification Methodology (Uvm)
- Public Speaking
- Labview
- C
- Programming
- Research
- Management
- C++
- Electronics
- Microsoft Word
- Team Leadership
- Systemverilog
- System Verilog
- Teamwork
- English
- Matlab
- Powerpoint
- Microsoft Excel
- Microsoft Office
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