Sandeep Shukla

WORK HISTORY

EDUCATION

SKILLS

ABOUT SANDEEP SHUKLA

My PhD is on theoretical analysis, complexity analysis and mapping of algorithmic aspects of formal verification. After my PhD, I worked in a telecommunications network management software lab where I developed distributed algorithms and their implementations for network management systems, and did research on middleware based distributed object technology. However, after 2 years in the telecom industry, I went back to my roots, and joined the formal verification team at Intel, working on the formal property verification of the ITANIUM processor microarchitecture, and while being at Intel, I took up interest in high level system modeling languages, simulation, and high level/behavioral synthesis. I was in a pilot team of experts for looking into various possible system design languages for a future generation IA64 processor design team. Eventually, I became a part of an IA64 Platform architecture group where I had to formally specify IA64 bus protocols and automatically generate checkers etc. In 2001, after 4 years of industry exposure, I decided to go back to academia. So I joined a post doctoral research associate position at the center for embedded computer systems at the University of California at Irvine. There, I started working on dynamic system level power management, IP composition for SoC design, formal methods for system design and other problems related to embedded system design. In fall 2002, I joined Virginia Polytechnic and State University as an assistant professor of computer engineering. My research lab is called FERMAT (Formal Engineering Research with Models, Abstractions and Transformations) whose website http://fermat.ece.vt.edu will provide more details of our research. Specialties: Teaching, Research, research supervision, project management, mentoring of students