Sandeep Ammula

About Sandeep Ammula

Currently working at Intel Corporation as Senior Engineering Manager & Tech Lead emulating XEON (server) SoCs and hands on architecting, leading Emulation Platforms functional cold reset bring up for single, multiple and multi socket dies. I am passionate about Computer Architecture and Digital Systems Design with 15+ years of professional experience in building and designing SoC/Embedded/FPGA products across Enterprise, Automotive, Security, and Medical Applications. Previously worked at Microchip Technology, developing cryptographic SoCs (ASIC Design) & FPGA prototyping, worked as a Technical Officer at Electronics Corporation of India (Govt of India) developing and Commissioning Access Control systems for Govt of India Federal sites. As a Research Assistant at Center for Robust Speech Systems(CRSS)/Cochlear Implant Lab,USA got an opportunity to develop FPGA based systems to advance Cochlear Research and to produce research papers/posters at sponsored conferences.

Experience

1. Senior Engineering Manager & Technical Lead

   Intel

   Jul 2025 — Present · Dallas, TX, US

   Managing high performing emulation model teams across multi-geographies.Champion of culture excellence and drive continuous process improvement through automation and usage of AIA strategic and an hands on results-driven leader with deep technical expertise in planning, architecting, and executing the reset bring-up of single and multi socket Diamond Rapids server processors on zebu and palladium emulation platforms.Proven ability to drive innovation, efficiency on emulators usage, debug across single-die (IO), multi-die (2 IO, Core + 2 IO), and multi-socket emulation models, ensuring seamless progression through all cold reset phases of xeon processor, including several cutting edge IPs, firmwares such as security, power management and BIOS and industry-leading IO interface (PCIE,CXL,DDR,UCIE, D2D etc) bring-up.Continuous improvement of emulation platforms through emulation platform vendor’s executive level interactions.Adept at leading and inspiring high-performing engineering teams, removing roadblocks, and driving the successful delivery of aggressive milestones with exceptional quality. Passionate about talent development through coaching, hiring, and mentoring the next generation of engineering excellence.

Education

• Nalanda Junior College

  High School Diploma, Mathematics, Physics and Chemistry

  2004 — 2006

• Indian Institute of Technology, Kharagpur

  Master's degree, Electrical, Electronics and Communications Engineering

  2011 — 2011

• KL University

  Bachelor's degree, Electrical, Electronics and Communications Engineering

  2006 — 2010

• The University of Texas at Dallas

  Master of Science (MS) Thesis, Digital systems design

  2016 — 2017

Skills

• Doors
• Vhdl
• Git
• Embedded C
• Python
• Canoe
• Xilinx Ise
• Cadence Virtuoso Layout Editor
• Keil
• Allegro
• Microsoft Office
• Orcad Capture Cis
• Uds
• Sketchup
• Embedded Software
• Verilog
• Perl
• Embedded Systems
• Code Composer Studio
• C
• Matlab
• System Verilog