Sandeep Vangala

About Sandeep Vangala

Leadership in technical roles with experience in developing multiple IP’s, Subsystems and delivery across several Server SOC’s. Extensive experience in implementation and verification of ASIC’s and defining validation strategies. Technical expertise in Pre-silicon verification, Emulation and post-silicon debug for IP developmentCollaborating across organizational boundaries and building working relationships.Core competencies-PCIe,Cache, Memory & IO Transaction and Link Layers,Computer Architecture-Mesh & Fabric interconnects, Non-coherent Main band and Side band fabric-DFT & DFD validation-Graphics Pipe3D & Texture Sampler-Re-usable pre-si verification infrastructure using OVM/UVM Methodologies -Emulation & Post-Si Debug-Execution with Cross site & Cross Functional Teams-IP/Subsystem/SOC Integration & Delivery.

Experience

1. Ip Design Manager

   Intel

   Nov 2019 — Present · Bengaluru, IN

   IP Design manager responsible for delivering high quality PCIe LogPhy IP (PCIe Gen5/6) across multiple generations. Leadership in driving transformation to deliver high quality IP while transitioning to industry standard tools and methodologies including SIP-Qualification, Industry standard BFM’s, Formal verification & UVM.

Education

• Osmania University

  Bachelor of Science - BS, Electronics and Communications Engineering

  1995 — 1999

• Wright State University

  Master of Science - MS, Electrical Engineering

Skills

• Formal Verification
• Vlsi
• Synopsys Tools
• Tcl
• Perl
• Computer Architecture
• Verilog
• Universal Verification Methodology (Uvm)
• Vhdl
• Soc
• Asic
• System on a Chip (Soc)
• Pcie
• C++
• Ovm
• Specman
• Xilinx
• Systemverilog