Sandeep Kumar

About Sandeep Kumar

I am a hardware engineer in the Electronic Design Automation (EDA) team at IBM, specializing in transistor-level timing analysis. My expertise spans the RTL-to-GDS flow, covering circuit design, static timing analysis, synthesis, floorplanning, placement, clock tree synthesis, routing, and timing closure with tools such as Cadence Virtuoso, Innovus, Tempus, and OpenLane. Backed by a M.Tech in VLSI & Embedded Systems Delhi) and a B.Tech in Electrical Engineering, I have worked extensively on digital and analog circuits, particularly in logic and physical design, through projects involving cell design, sense amplifiers, SoC implementations, and signal processing. I am proficient in Verilog, Python, Perl, TCL, and C programming, enabling me to contribute across logic design, verification, and hardware–software co-design challenges. Previously, I worked as a Mathematics Faculty at BYJU’S, where I honed my presentation, communication, and leadership skills, strengthening my ability to convey complex concepts with clarity and lead teams effectively. Passionate about chip design, circuit optimization, and EDA innovation, I aim to contribute to next-generation semiconductor solutions. Beyond engineering, I enjoy poetry, storytelling, singing, and sports. Actively building a professional network of 15k+ connections to exchange ideas and opportunities in semiconductor and technology fields.

Experience

1. Hardware Engineer

   IBM

   Jul 2025 — Present · Bengaluru, IN

Education

• Amar Memorial St. George School

  Intermediate

  2012 — 2014

• Madan Mohan Malaviya University of Technology

  Bachelor of Technology - BTech

  2015 — 2019

• FIITJEE

  Foundation

  2012 — 2014

• Prime classes

  Target IITJEE

  2014 — 2015

• Indraprastha Institute of Information Technology, Delhi

  Master of Technology - MTech

  2023 — 2025

• Delhi Public School - India

  High School

  2010 — 2012