Sandeep Chalasani
Design @Apple
- Role
- Design Engineer at Apple
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Design Engineer
Aug 2015 — Present · San Francisco, CA, US
Education
University of Utah
Masters
2007 — 2009
Vellore Institute of Technology
B.TECH
2003 — 2007
Skills
- Cmos
- Analog
- Cadence Virtuoso
- L-Edit
- Vlsi
- Computer Architecture
- Parasitic Extraction
- Jmp
- Powder X-Ray Diffraction
- Photonics
- Clean Rooms
- Pecvd
- Characterization
- Semiconductor Process
- Circuit Design
- Perl
- Eda
- Analog Circuit Design
- Mems
- Cadence
- Ic
- Assura
- Thin Films
- Sensors
- Sputtering
- Photolithography
- Calibre
- Soc
- Matlab
- Semiconductors
- Semiconductor Device
- Microfabrication
- Simulations
- Nanofabrication
- Drc
- Pdk Development
- Silicon
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