Sandeep Bhatia
DFx Lead for Google TPUs
- Role
- Dfx Lead Ml Asic Tpus at Google
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Sandeep Bhatia
Architect for Google TPU ASIC Design - focussing DFX (Test, Debug, Reliability and YIeld) Solutions. Leading development of Innovative custom Design & DFX solutions for challenging ASIC defects that can cause Silent Data Corruption. Extensive ASIC design experience to improve data center quality and reduce cost. Working closely with Hardware/Software design teams to develop various RAS features for HPC and ML systems at Google Data Center that help detect, diagnose and recover from various hardware defects at scale.Expertise in ASIC Design Flows - DFX, Synthesis, Verification, Low Power, CDC, Physical Design, Timing Closure, DFT/ATPG, Si BringupExperienced in Hardware/RTL design (System Verilog) and Software (Python, C++)
Experience
Dfx Lead Ml Asic Tpus
Sep 2013 — Present
Education
University of Rochester
M.S., Electrical Engineering
Indian Institute of Technology, Delhi
B. Tech., EE
Princeton University
Ph.D., Computer Engineering
Skills
- Low-Power Design
- Tcl
- Logic Synthesis
- C++
- Atpg
- Eda
- Soc
- Asic
- Vlsi
- Static Timing Analysis
- Dft
- Verilog
- Embedded Systems
- Rtl Coding
- Semiconductors
- Very-Large-Scale Integration (Vlsi)
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