Sandeep Bhardwaj
Design Verification Engineer
- Role
- Senior Staff Engineer at Marvell Technology
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Sandeep Bhardwaj
I am a highly skilled postgraduate with a robust background in Design Verification…
Experience
Senior Staff Engineer
Jun 2024 — Present · Bengaluru, IN
DDR-SS Verification
Education
Sagar Institute of Research Technology & Excellence, Bhopal
Bachelor's degree, Electronics and Communications Engineering
2008 — 2012
Devi Ahilya Vishwavidyalaya
Master of Technology, Embedded Systems
2014 — 2016
Beacon English School, Korba
10th, All Subject(Science)
2005 — 2006
Beacon English School, Korba
12th, PCM
2007 — 2008
Skills
- Cadence Virtuoso
- Mentor Graphics Questasim
- Systemverilog
- Layout Versus Schematic (Lvs)
- Application-Specific Integrated Circuits (Asic)
- Embedded C
- Perl
- Assertion Based Verification
- Systemverilog Assertion
- C
- Vhdl
- Shell Scripting
- Functional Coverage
- Static Timing Analysis
- Xilinx Ise
- Verilog
- Amba Ahb
- Aldec Reviera-Pro
- Design Rule Checking (Drc)
- Field-Programmable Gate Arrays (Fpga)
- Java
- Universal Verification Methodology (Uvm)
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