Sandeep Aranake

About Sandeep Aranake

I work in the area of electronic design automation (EDA) for VLSI circuits. Key area expertize: Design and implementation of electronic systems Scan synthesis Simulation and verification of electronic system System emulation using FPGAs Parallel computing and its use in implementation, verification and emulation Low power system design and synthesisCore strengths Computer Algorithms Digital design Logic optimization System performance analysis Object Oriented Design C and C++ UML & Design Patterns VHDL & Verilog Two publications Co-author of one patent

Experience

1. Software Engineer

   Synopsys Inc

   Aug 2004 — Present · Mountain View, CA, US

   Logic Synthesis, sequential optimization techniques such as retiming Synthesis under low power constraints, clock gating, UPF Timing and power analysis Experience in synthesis methodologies used in designing high end VLSI chips Design compiler, Power compiler, Prime Time C, C++, Object Oriented Design Algorithm design and implementation Scan synthesis

Education

• The University of Texas at Arlington

  Master’s Degree, Computer Science

  1991 — 1993

• Dr. Babasaheb Ambedkar Marathwada University, Aurangabad

  Bachelor’s Degree, Electronics Engineering

  1982 — 1986

• Institute of Technology (Banaras Hindu University), Varanasi

  Master of Technology (M.Tech.), Micro Electronics

  1986 — 1987

Skills

• Soc
• Debugging
• C
• Perl
• Eda
• Asic
• Verilog
• Software Design
• Tcl
• Processors
• C++