Sandeep Aggarwal
Project Manager, DFT/DFX Lead in VLSI Design, LTTS
- Role
- Project Manager Dft Dfx Lead in Ltts at L&T Technology Services
- Location
- Pune, IN
- LinkedIn followers
- 500 followers
About Sandeep Aggarwal
Having more than 15 years of expertise and a variety of responsibilities in the semiconductor industry Insight and knowledge of semiconductor device physics. Understanding of a wide range of cutting-edge technologies and procedures (for designing, fabricating, and testing). Super Junction Power Transistor BV range 250V-1200V design employing multiple technologies (Deep Trench, Multi Deep Trench, Double Implant, & Single Implant) for varied Cell Pitch. 6+ years of DFT experience with Mentor/Cadence tools with SCAN, ATPG, Compression, GLS, Boundary Scan, and MBIST. Different SiC semiconductor devices (MISFET, MESFET, SOI-MESFET, Double Gate MESFET, and Dual Gate MESFET) were designed and optimized. knowledge of the Spice Circuit Simulator and IC Layout tool, particularly for developing circuits including SRAM (6T), ADC, PLL (CMOS), and DPLL.
Experience
Project Manager Dft Dfx Lead in Ltts
Jul 2021 — Present · Mysuru, IN
Education
Jamia Millia Islamia
M.Sc (Electronics &Communication), Semiconductor Physics & Devices,Microwave,Analog Electronic, Circuit & System,Laser
1999 — 2001
Jamia Millia Islamia
Bachelor of Science (B.Sc.), PHYSICS(Hons)
1996 — 1999
Delhi University
Ph.D, Electronics
2003 — 2008
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