Sanchi Pathak

About Sanchi Pathak

I am a DFT professional in Google Bangalore GChips India with industry experience in end-to-end DFT implementation, DFT verification and multimode DFT STA constraint development along with flow automation in scripting languages like TCL/python for efficient DFT activities on complex projects.I have multiple project experience for on-time closure of following DFT activities under aggressive timelines :• DFT architecture creation for abutted and non-abutted SOC.• Chip level multimode DFT STA Constraint development along with establishing effective cross functional collaboration for smooth DFT timing convergence.• DFT test structure insertion including IJTAG P1687)/JTAG 1149, Scan Compression logic, clock/reset control logic and IP testing logic. • MBIST insertion and verification along with repair analysis.• Hierarchical/ flat Scan insertion with minimum area overhead.• ATPG pattern generation, pattern retargeting, verification and optimum coverage analysis for stuck, at-speed and iddq faults. • DFT Methodology and flow development along with practical experience in industry standard EDA tools like Tessent, TestKompress, Tempus, PrimeTime, SpyGlass, Cadence tools, Genus, Design Compiler, Questa.

Experience

1. Asic Design for Testability Engineer

   Google

   Nov 2022 — Present · Bengaluru, IN

Education

• Shri G S Institute of Technology & Science

  Bachelor of Engineering - BE, Electronics and Instrumentation Engineering

  2015 — 2019