Sanchika Aggarwal

About Sanchika Aggarwal

Experience & expertise in ASIC verification on all IP/VIP/SoC subsystem level. Strong knowledge of verilog, System verilog, UVM and C. Debugging is my top - notch skill.My work involves the verification testplan creation according to the design artifcats,UVM & SV based verification environment buildup /tests,SVA & functional coverage.Apart from having good hands on functional and formal verification, I have also expertise of gate level simulations and emulations on palladium platform for subsystem level usecases. Alongwith all of these, i have also worked on the processor verification for RiScv cores, multi-core SoCs, Debug-Trace unit verification and many more well known industrial communication protocols like USB,PCIE.I am keen to grow more technically into my profile and looking forward to enhance my skills.

Experience

1. Technical Lead

   HCLTech

   Jun 2020 — Present · Noida, IN

   Handling C based SoC verification projects alongwith Emulation activities (for NXP projects)

Education

• M.Tech (E&ES)

  M.TECH (ELECTRICAL & EMBEDDED SYSTEMS), ELECTRICAL INSTRUMENTS, EMBEDDED SYSTEMS, ELECTRONIC CIRCUIT DESIGNING

  2011 — 2013

• PDM College of Engineering - India

  B.TECH (INSTRUMENTATION CONTROL ENGINEERING), VLSI, VERILOG, PERL, C/C++,

  2007 — 2011

Skills

• Rtl Design
• Functional Verification
• Processors
• Microcontrollers
• Debugging
• Xilinx
• Systemverilog
• Logic Design
• Embedded Software
• Asic
• Physical Design
• Usb
• Vlsi
• Soc
• Verilog
• Device Drivers
• Spi
• Amba Ahb
• C
• Pcb Design
• Vmm
• Primetime
• Timing Closure
• Circuit Design
• Testing
• Integrated Circuit Design
• Microprocessors
• Rtos
• Tcl
• Open Verification Methodology
• Electronics
• Embedded C
• Ic
• Uvm
• Static Timing Analysis
• Digital Electronics
• Ncsim
• Veritas Cluster Server
• Vhdl
• Simulations