Sanat Konda

Digital Design Intern @Honeywell Technologies

Clearwater, FL, US

Designed and validated 10/25 Gbps transceiver links on Xilinx UltraScale+ devices, optimizing latency and signal integrity across multi-gigabit SERDES channels- Developed a custom runtime (XRT) and boot image to bring up FPGA platforms from bare metal, enabling deterministic networking pipelines tuned for high-frequency data paths- Built and tested high-performance networking stacks with hardware-accelerated protocol engines, achieving low-latency packet processing suitable for real-time trading and control applications- Designed a 4-layer high-speed digital board with controlled-impedance routing, differential pair tuning, power decoupling, and jitter-tolerant clock distribution for timing-critical domains- Automated FPGA build/test flows with Vivado TCL scripting and CI integration, cutting iteration cycles by 30%.