Samuel Pakalapati
CPU Performance @ Google | ex-Intel | Texas A&M | BITS Pilani
- Role
- Cpu Performance Architect at Google
- Location
- College Station, TX, US
- LinkedIn followers
- 500 followers
About Samuel Pakalapati
I worked as a CPU Performance Intern at Tenstorrent. I have invented and implemented novel data prefetching schemes for an RISC-V core in a C++ based performance model. I have also conducted deep debugging to understand the performance differences and future opportunities. In addition to my work on prefetching, I have a solid understanding of the memory subsystem as a whole, including caches, replacement and scheduling policies, and so on.I am excited about optimizing data movement in computer architecture, since the memory wall is still a significant barrier to increasing processor performance. My interests include performance modeling, workload analysis, and architecture space exploration.
Experience
Cpu Performance Architect
Jun 2025 — Present · Austin, TX, US
Education
Texas A&M University
Master of Science - MS
Birla Institute of Technology and Science, Pilani
Bachelor of Engineering
2014 — 2018
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