Samprithi Vilvasigamani
Logic Design Engineer at Parade Technologies, Inc.
- Role
- Logic Design Engineer at Parade Technologies, Inc.
- Location
- Beaverton, OR, US
- LinkedIn followers
- 500 followers
About Samprithi Vilvasigamani
I am a MS ECE graduate, with a focus in digital design and verification. I have developed skills in SystemVerilog, Verilog, UVM, protocol verification, and RISC-V processor design. During my internship at QuantSemicon, I gained hands-on experience building verification environments in SystemVerilog (UVM) for APB and AHB protocols, focusing on coverage closure and protocol compliance. My projects span AXI4 protocol design with UVM-based verification and RISC-V processor development, including pipelined and radiation-hardened architectures.
Experience
Logic Design Engineer
Sep 2025 — Present · Beaverton, OR, US
Education
University of Illinois Chicago
Bachelor of Science - BS, Electrical Engineering
University of Illinois Chicago
Master of Science - MS, Electrical and Computer Engineering
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