Sampath Naveen Padmanabhuni

About Sampath Naveen Padmanabhuni

I am a Technical Project Manager, System Integration Engineer and Hardware Design Engineer with over 7 years of experience in the semiconductor manufacturing domain. Currently, as a Senior Integration Engineer at ASML, I specialize in developing and integrating advanced systems for wafer inspection, including cutting-edge 3nm node technology. I have successfully led cross-functional teams to deliver optimized solutions for global clients like Intel, TSMC, Micron, and Samsung.My expertise includes hardware design, firmware integration, and system calibration. I’ve worked extensively on critical modules such as deflection image controllers, HV systems, and wafer alignment systems, ensuring reliability and performance through rigorous testing and troubleshooting. My contributions have enhanced system performance in high-stakes environments, both onsite and globally.With a master’s in electrical engineering from the University of South Florida, I bring a strong foundation in CMOS VLSI design, MEMS technology, and ASIC development. My hands-on project experience has honed my skills in tools like Cadence, Xilinx Vivado, LTSpice, and Intel Quartus Prime Programmer, alongside programming expertise in Python, MATLAB, and SQL.Driven by a passion for innovation and collaboration, I thrive in fast-paced environments where problem-solving and technical leadership are key. I aim to contribute to the advancement of semiconductor technology while fostering impactful client and team collaborations.

Experience

1. Technical Project Manager

   ASML

   Dec 2024 — Present · US

Education

• University of South Florida

  Masters, Electrical engineering

• Sathyabama University

  Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering

  2013 — 2017