Samith Sasikumar
SoC/RTL Design Engineer at Cadence Design Systems | MSE Electrical Engineering at ASU
- Role
- Lead Soc Rtl Design Engineer at Cadence
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Samith Sasikumar
With a passion for innovation, collaboration, and excellence in engineering, I am pursuing my Master\'s degree in Electrical and Electronics Engineering at Arizona State University (ASU), focusing on digital design and computer architecture. I aim to apply my knowledge and skills to solve real-world problems and challenges in the field of ASIC/FPGA design and development, and to learn new technologies and tools that can enhance my expertise and career prospects.Previously, I was an RTL Design Engineer at Tata Elxsi, a leading global design and technology services company. I spearheaded multiple FPGA design projects for wireless communication and signal processing systems, using Intel and Xilinx devices. I specialized in RTL coding, simulation, synthesis, testbench development, scripting, and IP implementation. I also designed and integrated FPGA-based systems with other hardware components, such as ADCs, DACs, and RF transceivers. I demonstrated proficiency in VHDL and Verilog languages, as well as communication protocols and signal processing modules. I contributed to improving the performance, quality, and reliability of the FPGA products and solutions.
Experience
Lead Soc Rtl Design Engineer
Feb 2024 — Present · Austin, TX, US
Design and integration of CPU and System IP for ARM and RISC-V architectures
Education
Arizona State University
Master's degree, Electrical and Electronics Engineering
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.