Saminathan Chockalingam

About Saminathan Chockalingam

Meticulous Execution: Consistently delivers high-quality results on time, regardless of complexity- ASIC SoC Expertise: Successfully designed and implemented Subsystem IP in 8+ ASIC SoC tape-outs, optimizing Power, Performance, and Area (PPA) using industry-standard EDA tools in advanced technology nodes- Extensive Experience: Over 16 years in front-end SoC ASIC RTL design and subsystem design, proficient in Lint, CDC, RDC, DFT, Simulation, Synthesis, PTPX power estimation, LEC, STA, PnR, and AC Timing Analysis- Micro-Architecture Expertise: Developed detailed micro-architecture specifications for SoC and hardware accelerator (HWA) blocks, ensuring optimal PPA- Network on Chip (NoC) Design: Specialized in NoC design with Sonics and Arteris toolsets- DSP and RTL Development: Extensive experience with DSPs, including Tensilica cores, and proficient in RTL development for DSP algorithms and IP core development- Hardware Accelerators for Computer Vision: Developed accelerators for tasks like image processing, SLAM, eye-tracking, and more, enhancing AR/VR applications- Audio Processing Pipelines: Implemented audio pipelines for ultra-low power wearable devices, integrating interfaces like Bluetooth, MIPI-SoundWire, and ultrasonic sensors- Advanced Graphics Functions: Enhanced graphics processing through expertise in RTL design for image bifurcations, interpolation, and texture mapping- Signal Processing Components: Developed DSP IP cores for FFT/iFFT, Turbo Encoder/Decoder, and MIMO systems, contributing to 5G/4G and other projects- IP Integration and Evaluation: Extensive experience in 3rd party IP integration, throughput analysis, and AC timing closure for IO interfaces- Power Estimation Proficiency: Skilled in power estimation using Synopsys PrimeTime PX, ensuring accurate assessments for complex SoC and Subsystem designs- 5G and Video CoDec SoCs: Contributed to the front-end design of 5G eNodeB L1-UL ASIC and FPGA prototyping, as well as high-speed peripheral SoCs- Clock and Reset Management: Designed clock domain crossing adapters, clock muxes, and memory components for SoC and Subsystem IP Design- Protocol Integration: Integrated protocols like AHB, APB, AXI, OCP and Q-Channel, with experience in UPF for power-aware verification- SoC Prototyping Expertise: Led FPGA prototyping for SoC designs using Altera and Xilinx devices, with a strong focus on board-level testing and debugging.

Experience

1. Digital Design Engineer

   Meta

   Feb 2018 — Present · Sunnyvale, CA, US

   Low Power Audio, Computer Vision, ML Hardware Accelerator (AI Inference Engine) Design

Education

• Shanmuganathan Engineering College - Anna University

  Bachelor of Engineering (BEng), Electrical and Electronics Engineering

  2003 — 2007

• S M S V Hr Sec School

  HSC, Maths, Physics, Chemistry and Biology

  2001 — 2003

Skills

• Debugging
• Xilinx
• Haps Protocompiler
• Vlsi
• Verilog
• Mimo
• Xilinx Ise
• Fpga Prototyping
• Lte
• Fpga
• Asic
• Rtl Design
• Altera Quartus
• Vhdl
• Digital Signal Processors
• Systemverilog for Design