Sameer Saurabh Singh
Design Verification Engineer at Meta
- Role
- Design Verification Engineer at Meta
- Location
- Redmond, WA, US
- LinkedIn followers
- 500 followers
About Sameer Saurabh Singh
I work as Pre-Silicon Verification Engineer at Meta. I have done MS in Computer Engineering from North Carolina State University Raliegh. My Field of interest includes ASIC verification/design, Computer Architecture.
Experience
Design Verification Engineer
Sep 2024 — Present · Redmond, WA, US
Education
Manipal Institute of Technology
Bachelor of Engineering (BE), Electrical and Electronics Engineering
2010 — 2014
North Carolina State University
Master of Science (MS), Computer Engineering
2016 — 2017
BSF Senior Secondary Residential School, Siliguri
CBSE
2006 — 2010
Skills
- Assembly Language
- Codesys
- Simulink
- Modelsim
- Teamwork
- Microsoft Office
- Universal Verification Methodology (Uvm)
- Cadence Virtuoso Layout Editor
- Synopsys Tools
- Verilog
- Pspice
- H-Spice
- Rtl Design
- Vhdl
- Keil
- Electronics
- Application-Specific Integrated Circuits (Asic)
- Matlab
- Ni Labview
- Perl
- Cadence Virtuoso
- C++
- System Verilog
- Ansys
- 8051 Microcontroller
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