Samarth M H

About Samarth M H

1.Acquired in-depth knowledge about the multiple stages in Semi-custom ASIC Design flow from specification to tapeout. 2.Understanding about gate level netlist, logical libraries, modes, PVT corners, timing scenarios, constraints, physical reference libraries(DEF, LEF), technology files. 3.Worked on floorplan where placement of hard macros was done based on dataflow diagram, dataflow flylines, and macro placement guidlines. 4.Worked on powerplan where width, spacing, pitch and offset of the pg wires had to be set, to have the IR drop within the maximum IR drop value. 5.Experience in solving pg DRV\'s, missing via violations, floating wire violations, creating standard cell rows and placing the boundary cells,tap cells in the core area. 6.Understanding about the filler cells, tap cells, boundary cells, decap cells, tie cells, clock gating cells, spare cells, DFT, scan chain, OCV, AOCV, crosstalk. 7.Understanding different stages involved in standard cell placement(coarse placement, scanchain optimization, DRC fixing, HFNS, timing driven placement, legalisation) 8.Understanding about CTS, routing, physical DRC\'s, logical DRC\'s and analysing reports generated at multiple stages of APR flow. 9.Hands on experience in Synopsys ICC2, PrimeTime and have understood and modified TCL scripts to solve issues faced in the APR flow. 10.Good understanding about logic design, MOSFET, fabrication process, Short channel effects, CMOS circuits, verilog.

Experience

1. Soc Design Engineer

   Intel

   Jul 2022 — Present · Bengaluru, IN

Education

• RV-VLSI Design Centre

  Advanced Diploma in ASIC Design

  2021 — 2022

• Arizona State University

  Master of Science - MS

  2025

• BNM Institute Of Technology

  Bachelor of Engineering - BE

  2017 — 2021