Salman Azam

Senior Hardware Engineer - Dft, Physical Design @Dreambig Semiconductor Inc

San Jose, PK

Chip & Package Level DFT• Led DFT architecture and implementation for a 4 nm, 2 GHz monolithic SoC featuring EBSCAN, MBIST, ScanCompression, OCC, and ATPG using Tessent, ensuring high coverage and robust testability.• Defined hierarchical, tile-based DFT methodology leveraging SSN; architected DFT connectivity across 46 blocks to create a scalable, reusable framework adaptable to future chiplet-based designs.• Integrated DFT for complex IPs including ARM Neoverse CMN700, ARM CPUs, SERDES, and PCIe, aligningvendor requirements for test access.• Collaborated with global STA, synthesis, and physical design teams to achieve MBIST timing closure at 2 GHz;verified post-insertion integrity through Formality LEC.• Optimized physical layout for DFT through memory clusterization and MBIST floorplanning to achieve under 70% area utilization. Oversaw automated scripts that reduced planning and execution effort by 50%.• Contributed to the development of a multi-die SSN-based DFT architecture for chiplet-based systems, supporting future heterogeneous integration.• Partnered with the Board Design team to define and finalize SSN and JTAG pinout requirements at both chip and package levels, ensuring seamless test access.Mentoring & Leadership• Delivered internal training sessions to design teams on making RTL test-friendly through DFT planning,methodology, reuse, and scan-based design integration.• Mentored junior engineers in advanced DFT implementation:∗ Oversaw OCC insertion across complex multi-clock domains and coordinated PLL control via Tessent TDRsfor at-speed scan and MBIST testing.∗ Guided development of margin control mechanisms using custom BISR registers and TDRs, enabling OTPfusing of calibrated values to recover otherwise defective devices.

The Community College of Baltimore County

Associate's degree

University of Maryland

Bachelor's degree

University of Maryland

Master of Science - MS