Salil Sahasrabudhe
Design Verification Manager @Apple
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WORK HISTORY
Design Verification Manager @Apple
Cambridge, GB
EDUCATION
Nanyang Technological University Singapore
MS, Integrated Circuit Design
Technical University of Munich
MS, Integrated Circuit Design
Savitribai Phule Pune University
Bachelor of Engineering (B.Eng.), Electronics Engineering
SKILLS
ABOUT SALIL SAHASRABUDHE
20+ years industry experience with the majority of it on CPU/GPUAt Apple:Design Verification ManagerAt Imagination:Oversaw CPU verification department including:Recruitment, resource planningEDA tool evaluationDefined Verification Strategy and architectureLed cross site team of 45 DV engineersMethodology and flow improvementsAt Arm:Oversaw multiple shared testbenches (Fetch, Execute, Memory system) across A-class CPUs.Technical lead for memory system verification of Arm’s latest A510 and A520.Technical lead for L2 cache verification of Arm’s A55 CPU.Verification assessor on Arm Ethos-77 NPULine manager to hierarchy of 18 individuals.
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