Salehabibi Shaikh
Lead DV Engineer @ Cadence Design System
- Role
- Lead Design Verification Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Salehabibi Shaikh
In my current role as a verification Engineer in Cadence Design System, I am responsible for UCIe IP Verification line.I have experience in UCIe with PCIe protocol layerExperienced IP Verification Engineer with a demonstrated history of working in the VLSI industry. Skilled in Universal Verification Methodology (UVM), SystemVerilog, C (Programming Language), C++, and Verilog. Strong engineering professional with a Master of Technology - MTech focused in microelectronics from BITS Pilani.
Experience
Lead Design Verification Engineer
Apr 2023 — Present · Bengaluru, IN
Education
Birla Institute of Technology and Science, Pilani
Master of Technology - MTech, Microelectronics
Nirma University
Bachelor of Technology - BTech, Electronics and communication
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