Salauddin Mohammed

About Salauddin Mohammed

Post Graduation in Micro Electronics and VLSI from Indian Institute of technology Madras,14+ Years of Hands-on Experience in ASIC/SOC Sub-System level and Sub-HM Level Physical Implementation from RTL to GDS. Technologies Worked: 10nm. 14nm, 22nm, 28nm, 32nm, 45nm Physical Implementation of Hierarchial Sub-Systems and Sub-HM’s ranging from 600k to 1.8M+ Instance counts with 75% to 80% Final Utilization. Floor Planning, Memory Placement, Power Plan, CPF/UPF Based Multi Power Domain PNR Implementations. Custom Clock Tree Implementations for High-Speed 2+GHz CPU Cores. Customized Clock Skew/Insertion Delay Optimizations for 500MHz+ Sub-HM’s. Low Power Flow: UPF/CPF Based Custom ISO/Always-On Cells’ Placement and Checks. MultiMode-MultiCorner Based PNR Implementations, MultiCorner RC Extraction using Star-RC. Signal Integrity Issues/Analysis- Cross-Talk Noise/Delay, AOCV & Electromigration. Tweaker Timing ECO Generation & PNR Implementations. MultiMode-MultiCorner Signoff Timing Analysis/Closure for Sub-HM’s & Hierarchical Sub-System: Complete Physical Verification for Sub-HM’s & Hierarchical Sub-System: DRC/ERC/LVS Closure: Formal Verification & Conformal Low Power Checks & Fixes. Static & Dynamic IR Drop Fixes.Standard cell library characterization and development for different IBM nodes: Characterization of complex cells using Power spice simulations and Quality checks using real Designs.

Experience

1. Senior Soc Lead Engineer

   Intel

   Aug 2020 — Present · Penang, MY

Education

• Indian Institute of Technology, Madras

  Master of Technology (M.Tech.), Micro electronics and VLSI

  2008 — 2010

• Osmania University

  BE, engineering

  2004 — 2008