Sakthivel Ramaiah

Design Engineering Architect at Cadence Design Systems.Director of Formal Verification in Interface Controllers - SSG/CSG.

Role
Design Engineering Architect at Cadence
Location
Bengaluru, KA, IN
LinkedIn followers
500 followers

About Sakthivel Ramaiah

I have 18+ years of experience spanning Formal Verification and Functional Verification, with deep technical expertise in the verification of complex interface controllers. Over the past 6 years, I have been dedicated to Formal Verification, leading a passionate team that delivers formal sign‑off solutions across high‑speed serial interface IPs—including USB, PCIe, CXL, and UALink. My work includes developing verification strategies, building scalable formal infrastructures, mentoring engineers, and driving adoption of advanced formal methodologies across project teams.I have published multiple technical papers at global conferences such as DAC, DVCon India/Europe/US, and JUG US, focusing on cutting‑edge formal techniques and sign‑off methodologies.Before transitioning fully into formal, I spent 12+ years working extensively on USB products ranging from USB 2.0 to USB4, serving as a USB Verification Architect at Cadence Bangalore. In that role, I architected SV/UVM‑based verification environments, guided feature bring‑up across multiple generations of USB products, and collaborated with cross‑functional teams to ensure robust verification quality.

Experience

  1. Design Engineering Architect

    Cadence

    Jul 2023 — Present · Bangalore Urban, IN

    Built and leading a passionate Formal Verification team for Interface Controllers including USB, PCIe, CXL, and UALink IPs. Standardized formal methodologies and automation scripts to enhance verification processes across multiple IPs. Organized and conducted the CSG Formal DV Summit for 2023, 2024, and 2025, promoting learning, best practices and inter-team collaboration.Strategized and Architected MDV TB Architecture for USB4 Router Verification and eusb2v2 Verification. Collaborated with UVM experts for scalability.

Education

  • National Institute of Technology, Tiruchirappalli

    Bachelor of Technology - BTech, Instrumentation and control

    2000 — 2004

  • College of Engineering, Guindy

    Master of Engineering - ME, VLSI Design

    2006 — 2008

Find verified contacts for anyone on LinkedIn

Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.

Free plan included · No credit card required

This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.

Sakthivel Ramaiah — Design Engineering Architect at Cadence in Bengaluru, KA, IN | Unifers