Sakthi Jegadish
principal solutions engineer in Cadence
- Role
- Senior Principal Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sakthi Jegadish
WORK EXPERIENCEHave 14+ Year’s of experience in Physical Design.Areas of ExpertiseWorked on block level RTL to GDSII delivery.Worked on block level timing closure in static timing analysis.Worked on block level PV signoffs like DRC/LVS/Antenna fixes.Worked on EMIR analysis and fixes in voltus.Worked on various technologies like 2nm, 3nm, 5nm, 7nm,16nm, 22nm, 28nm, 40nm, 45nm, 65nm.SKILLS(tools, language, domain)Synthesis : DC, genusPNR : Innovus, ICC2Extraction: Star RC, quantusVerification Tools : Calibre (DRC & LVS)Static Timing Analysis : PT, TempusEMIR: voltusScripting Language : Perl and TclPlatform: Linux, Windows
Experience
Senior Principal Engineer
Jan 2025 — Present · Bengaluru, IN
Education
John the Baptist Higher Secondary School
HSC, Mathematics
2000 — 2007
John the Baptist higher secondary school
HSC, Maths,Biology
2005 — 2007
S.a.engineering College
Bachelor of Engineering (BE), CSE
2007 — 2011
Skills
- Asic
- Formal Verification
- Vlsi
- Rtl Coding
- Functional Verification
- Soc
- Ncsim
- Systemverilog
- Rtl Design
- Physical Design
- Logic Synthesis
- Lvs
- Eda
- Verilog
- Static Timing Analysis
- Cmos
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