Sakshi Gupta
Design Engineer intern @Cadence || M.TECH (VLSI) NIT DELHI(24-26) || BTECH(ECE) CURAJ(20-24)
- Role
- Intern Design Engineer at Cadence
- Location
- Jaipur, RJ, IN
- LinkedIn followers
- 500 followers
About Sakshi Gupta
Hii, I am pursing my post graduation in VLSI and hand on experience of Cadence virtuoso tool.I have basic knowledge of Xilinx Vivado, Tanner, and Verilog,HFSS.Passionate about leveraging technology to solve real-world problems, I am open to collaboration and always eager to learn and grow. Let\'s connect and explore opportunities together!Thank you for visiting my profile, and I look forward to engaging with fellow professionals, recruiters, and enthusiasts in the tech community.
Experience
Intern Design Engineer
Jun 2025 — Present · Noida, IN
Working on SERDES receiver front-end analog blocks with focus on performance optimization.• Performing circuit analysis, simulation, and optimization using Cadence Virtuoso.• Also Involved in design and implementation of receiver front-end circuits including CTLE to meet target specifications and also current mirror, two stage Opamp.• Working on improving key performance parameters such as gain, noise performance, bandwidth, and power consumption.
Education
Vandana Academy Sr. Sec. School
12, Pcm
National Institute of Technology Delhi
Master of Technology, Electrical, Electronics and Communications Engineering
National Institute of Technology Delhi
Master's degree, VLSI Engineering
Central University Of Rajasthan
Bachelor of Technology, Electrical, Electronics and Communications Engineering
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