Sakshi Gangwar
(Immediate Joiner) Senior Verification Engineer (VLSI) at HCL|| M.Tech.(C&I),DTU Delhi
- Role
- Senior Verification Engineer (Vlsi) at HCLTech
- Location
- Delhi, IN
- LinkedIn followers
- 500 followers
About Sakshi Gangwar
Technical Proficiencies Include: HDL: Verilog HVL: SystemVerilog VERIFICATION METHODOLOGY: Constraint Random Coverage Driven-Verification | Assertion Based Verification - SVA TB Methodology: UVM( Universal Verification Methodology) EDA TOOLS:Xilinx ISE 14.7, Modelsim, Mentor Graphics-Questasim, Intel Quartus Prime, Synopsys VCS DOMAIN: Front-end Design and Verification Protocols : SPI, eSPI, I2C PROGRAMMING LANGUAGES: C[Datatype Array | Pointers List Memory Allocation | Functions]|| Oops Concepts, Inheritance, Polymorphism, Encapsulation OPERATING SYSTEMS:Linux, Windows CORE SKILLS:[RTL Verification using constrained randomization | Assertions based Verification | Regressions | Bug Identification | Analyzing waveforms using DVE | Code Coverage]
Experience
Senior Verification Engineer (Vlsi)
Sep 2021 — Present · Bangalore, IN
Education
Delhi Technological University (Formerly DCE)
Master of Technology - MTech
2018 — 2020
JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA
B.Tech.
2014 — 2018
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