Saketh Reddy
MTS Silicon Design Engineer, AMD
- Role
- Mts Silicon Design Engineer at AMD
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Saketh Reddy
Physical Design Engineer have experience in RTL2GDS flow. Worked on 3, 4nm and 5nm technologies. Leading approximately 10Million instance count complex Sub systems and working with cross functional teams. Good in calculating area requirement, top level partitioning and discussing with full chip team. Good at solving critical congestion issues and implementing complex CTS, routing and eco generation. Understanding cross talk, noise fixing methodology and implementation
Experience
Mts Silicon Design Engineer
Nov 2025 — Present · Hyderabad, IN
IP lead owning from Synthesis, PnR, STA till gds
Education
Manipal Institute of Technology
Master's Degree, Microelectronics
2014 — 2016
Skills
- Microsoft Office
- Cadence Encounter
- Cadence Rtl Compiler
- Synopsys Primetime Px
- Redhawk
- Low-Power Design
- Cadence Innovus
- Synopsys Primetime
- Windows
- Cadence Tempus
- Unix
- Design Compiler (Dc)
- C
- Icc Ii
- Verilog
- Powerpoint
- Microsoft Excel
- Perl
- Microsoft Word
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