Saketh Kumar M
Design engineer 2 @Cadence Design systems
- Role
- Design Engineer Ii at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Saketh Kumar M
Physical Design Engineer with over 2 years of experience in advanced nodes at Cadence Design Systems, specializing in sub-5nm technologies. Experienced in working with high-speed interface IPs such as SerDes, PCIe, and UCIe as part of complex testchip development.Proficient in floorplanning, power grid definition, clock tree synthesis, and static timing analysis (STA) to achieve optimal performance, power, and area (PPA) targets. Skilled in ECO implementation, congestion resolution, and DRC/LVS signoff, ensuring clean and manufacturable layouts.Contributed to the die model generation for advanced testchip packages, aligning physical design deliverables with packaging constraints and collaborating effectively with cross-functional teams.Hands-on experience with industry-standard tools including Cadence Innovus, Tempus, Voltus, and Pegasus, with a strong focus on timing closure, power integrity, and signoff accuracy at leading-edge technology nodes.
Experience
Design Engineer Ii
Jan 2026 — Present · Bengaluru, IN
Education
Birla Institute of Technology and Science, Pilani
Master of Technology - MTech
CVR College of Engineering, Hyderabad
Bachelor of Technology - BTech, Electronics and Communications Engineering
2019 — 2023
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