Saket Kumar
Associate Verification Enginneer @Semtech
Bhubaneshwar, OD, IN
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WORK HISTORY
May 2015 — Present
Associate Verification Enginneer @Semtech
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Bhubaneshwar, IN
PCIe Physical layerAHB overrides RTL codingTEST Bus RTL CodingAHB Overrides and Test Bus verificationSystem VerilogFormality CDC fixingLINT fixesPython scripting
EDUCATION
2008 — 2010
D.A.V Public school Hehal ,Ranchi
High School
2011 — 2015
National Institute of Science and Technology (NIST), Berhampur
Bachelor of Technology (B.Tech.)
ABOUT SAKET KUMAR
1+ years of experience in ASIC Design and VerificationHDL - VerilogHVL - System VerilogProtocols - PCIe PHYEDA tools - NcVerilog, VCS,Questasim,PrimeTime, Spyglass CDC Tool, Formality Tools
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