Sajjad Pagarkar

About Sajjad Pagarkar

A visionary and results-driven executive leader with 26 years of deep expertise in global semiconductor operations, specializing in end-to-end product development, manufacturing, and supply chain excellence for cutting-edge mobile and AI Tensor Systems-on-Chip (SoCs).I have spearheaded the complete lifecycle of semiconductor operations at Google and Qualcomm, from sourcing and development with foundries and OSATs to high-volume manufacturing (HVM). This includes building and leading the critical teams and infrastructure for Post-Silicon activities, encompassing Design Validation, DFT Productization, CPU-GPU-TPU-DSP-Ambient computing & HSIO Characterization, Power & Performance Optimization, System Correlation, Chip Qualification, and the development of high-volume manufacturing ATE & SLT screening solutions. My leadership has consistently driven yield improvement, RMA Triage, and sustaining productization.Notably, I successfully enabled the high-volume manufacturing of Google\'s Tensor System-on-Chip (SoC), a testament to my ability to deliver groundbreaking products to market. Throughout my career, I\'ve managed the successful productization of over 23 complex SoCs, from 28nm to 3nm FinFET and 2.5D CoWoS architectures. As Chief of System Level Test Engineering, I architected a state-of-the-art SLT system that delivered a 40x increase in throughput at one-fifth the cost of previous generations, directly translating into significant gains in scalability, cost-efficiency, and delivery performance.My career progression from individual contributor to Senior Director of Technology reflects a pragmatic approach to innovation, a commitment to technical detail, and a consistent ability to drive business solutions by anticipating and adapting to evolving needs. Passionate about leveraging advanced technology to deliver unparalleled operational excellence, I am adept at providing clear strategic direction and fostering a culture of high performance and continuous improvement across all organizational levels.

Experience

1. Senior Director, Chief of Silicon Engineering,

   Google

   Dec 2019 — Present · San Diego County, CA, US

   I am a pioneer in post-silicon NPI engineering, specialized in building end-to-end functions for complex Mobile, Compute, and AI SoCs from the ground up. By bridging the gap between architecture, design, and high-volume manufacturing (HVM), I transform ambitious silicon concepts into market-ready products.Core CompetenciesOrganizational Building: Established entire post-silicon departments where none existed. Recruited and scaled elite, multifaceted teams across DFT, DV, Test, Product Engineering, SLT, and HSIO/AMS Characterization.Technical Lifecycle Ownership: Directed the full spectrum of post-silicon activities, including:Silicon Bring-up & Validation: Design validation & Process Tuning.Characterization: Deep-dive analysis of CPU, GPU, TPU, DSP, HSIO, and Power/Performance.System Optimization: Tuning HW-SW integration to maximize Power-n-Performance (PnP) and driving system-level correlation.HVM Execution: Innovating ATE & SLT screening, yield enhancement, and RMA triage.Strategic Global Sourcing: Led end-to-end development and manufacturing engineering for Google’s Tensor SoC, managing critical partnerships with foundries and OSATs.Executive Leadership & Impact: I align technological innovation with revenue objectives, ensuring best-in-class quality without losing sight of technical depth.Budgetary Authority: Owned the full product-development-budgetCross-Functional Influence: Served as a pivotal voice in educating architecture, DV, and software teams on manufacturing considerations, embedding \"Design for Excellence\" into the development lifecycle.Collaborative Execution: Leveraged high emotional intelligence and strong communication to navigate complex vendor relationships and internal stakeholder alignment.I deliver robust execution frameworks for the world’s most advanced SoCs. Whether scaling a team of experts or managing multi-million dollar manufacturing budgets, my focus remains constant: innovation, quality, and scalable results.

Education

• University of Mumbai

  BE, Elecronics Engineering

  1987 — 1991

• UC San Diego

  Six Sigma Black Belt

  2005 — 2006

• UC San Diego

  Lean Enterprises, Efficiency and Quality improvement

  2004 — 2005

• Stanford University

  Stanford Advance Project Management, Project Management

  2005 — 2007

• Portland State University

  MS ECE, Electrical and Computer Engineering

  1998 — 1999

Skills

• Slt
• Processors
• Cmos
• C
• Ate
• Digital Signal Processors
• Customer Quality
• System Level Test
• Wireless
• Testing
• Engineering
• Microprocessors
• Ic
• Product Development
• Embedded Systems
• Eda
• Cdma
• Test Architecture
• Debugging
• Lte
• Vlsi
• Soc
• Production Screen
• Arm
• Mobile Devices
• Fpga
• Asic
• Cpu Characterization
• Semiconductors
• Characterization
• Test Strategy
• Wcdma
• Post Silicon Validation
• Test Director
• Mixed Signal
• Customer Engineering