Sajeel Abid

About Sajeel Abid

Bachelor’s student in Electronics and Communication Engineering and a passionate VLSI enthusiast, actively building expertise in RTL design and functional verification. I am continuously learning and evolving in the design and verification domain, with a strong focus on writing clean RTL, developing robust testbenches, and applying industry-standard verification methodologies.I am proficient in Verilog, SystemVerilog, UVM, SVA (Assertions), functional and code coverage, RTL design, and Perl scripting. I have hands-on experience with industry-level EDA tools such as QuestaSim, Xilinx Vivado, Synopsys VCS, and Synopsys VC SpyGlass, along with foundational knowledge of Linux, Operating Systems, and Computer Networking.I am currently undergoing advanced training in RTL Design and Verification at Maven Silicon Private Limited, where I progressed from core fundamentals to practical implementation through multiple mini-projects. These include 1×3 Router RTL Design, 1×3 Router Verification using UVM, and Mod-12 Counter Verification using SystemVerilog, providing me with real-world exposure to design, simulation, debugging, and verification workflows.Detail-oriented and committed to continuous professional growth, I am seeking fresher / entry-level opportunities in the VLSI Design and Verification domain where I can contribute to building reliable silicon—recognizing chips as a driving force of the global FutureTech ecosystem.My project repositories are available on GitHub, reflecting my learning journey and hands-on work. I am open to discussions, collaborations, and relevant opportunities.

Experience

1. Content Writer

   Medium

   Apr 2025 — Present · Bengaluru, IN

   Create technical content focused on digital logic design, RTL coding, and verification. Explain concepts related to combinational and sequential logic in a clear, beginner-friendly way. Develop RTL implementations and corresponding testbenches using Verilog and SystemVerilog. Document mini-projects and real-world applications of digital design. Share insights on verification methodologies using SystemVerilog and UVM. Use industry-standard tools to demonstrate simulation, debugging, and verification workflows. Simplify complex VLSI concepts to help learners understand them easily. Use writing to maintain consistency, track progress, and contribute to the VLSI learning community.

Education

• Minto Circle School

  PCM

• SSM College of Engineering

  B.Tech, Electrical, Electronics and Communications Engineering