Sajan Sahili

About Sajan Sahili

Mixed Signal VLSI Circuit Designer,with a Masters degree, seeking full time opportunities in the field of Digital circuits,ASIC design Verification,Analog Circuits and RF Transceiver Design. Experienced in doing both custom layout design and APR (auto place and route) based physical design using Cadence Virtuoso,Cadence Encounter and Primetime EDA tools, Hardware Design & Verification Languages, Advanced Analog Integrated Circuit design and VLSI High-Speed I/O Circuits and RF Transceiver Circuits.• Design & Simulation Tools: IBMRF7, Silvaco Devedit & Deckbuild, MATLAB(simulink).• HDL Languages: Verilog, System Verilog.• Simulation Tools: Modelsim, Aldec Riviera pro, Active HDL.• EDA Tools: Primetime,Design Compiler,RTL Compiler for syntheis,Hspice,StarRc,Cadence Virtuoso,Cadence Encounter (RTL to GDSII),Starrc,Cadence ELC.• Programming: C/C++, Unix shell scripting,Perl,Python, Tcl.Solid foundation in VLSI High-Speed I/O Circuit design including design of PLL, VCDL & VCOs with focus on Delay Minimization (optimized P/N ratio, optimal Fan-out), Jitter reduction, Phase Interpolation, T-Line termination and Adaptive tracking.Good understanding in RF Transceiver circuits like Low Noise Amplifiers and Mixers with expertise in RF Layout techniques.

Experience

1. Principal Product Engineer

   Cadence

   Jun 2019 — Present · San Jose, CA, US

Education

• Arizona State University

  Master's degree, Electrical and Electronics Engineering

  2013 — 2015

Skills

• Latex
• Java
• Semiconductor Device
• Verilog-a
• Modelsim
• Design Verification Testing
• High Speed I/O Design
• Html
• Rf Design
• Asic
• C++
• C
• Simulink
• Silvaco
• Cadence Virtuoso Layout Editor
• Cadence Soc Encounter
• Microsoft Office
• Vlsi
• Cadence Virtuoso
• Digital Circuit Design
• Matlab
• Powerpoint
• Microsoft Excel
• Analog Circuit Design
• Microsoft Word
• Verilog
• Synopsys Primetime
• Hspice
• Cadence Spectre
• Star-Rcxt