Sajan B.
Physical Design Engineer @ Qualcomm, Noida || M.Tech- VLSI @ NIT Delhi, Delhi || B.Tech- ECE @ IGIT, Odisha
- Role
- Physical Design Engineer at Qualcomm
- Location
- New Delhi, DL, IN
- LinkedIn followers
- 500 followers
About Sajan B.
Presently working as Physical Design Engineer at Qualcomm.Having 4+ year of effective VLSI Physical Design experience in latest tech node like 2nm, 3nm and 4nm with macro packed, multi-million gate, multi-voltage design. Implementing cutting edge design tech, resulting in significant area and power saving.Good understanding and knowledge on most aspect of backend ASIC design flow- Work on Floorplan, Placement, CTS, Route, implementing ECOs in lower techn node like 2nm, 3nm and 4nm- Implementing custom clock H-tree, MSCTS as per block requirement- Timing closure for noise analysis, xtalk optimization- Implementing FV, CLP, PDN, STA feedback from block and SOC POC.A collaborative team player with excellent communication and problem solving skill. Adaptive and self-learner.Interested in PD and STA profile
Experience
Physical Design Engineer
Jun 2023 — Present · Noida, IN
Education
National Institute of Technology Delhi
Master of Technology - MTech, VLSI
2021 — 2023
MBS Public School, Bhubaneswar
Higher Secondary School
2013 — 2015
Indira Gandhi Institute of Technology, Sarang
Bachelor of Technology - BTech, Electronics and Telecommunication
2015 — 2019
Carmel English Medium School, Phulbani
Matriculation
2001 — 2013
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