Sai Teja Gorantla

About Sai Teja Gorantla

STA/Full Chip Timing- Handled Timing Closure and related activities of high frequency designs at both chip and block level at below 5 nm tech nodes- Well versed with debugging and resolving violations for Timing Convergence in various Modes and Corners [DMSA]- Have great understanding of clock architecture and deep sub-micron design issues such as cross talk, ocv, aocv, pocv etc- Familiar in collaborating with design, DFT and PD teams and resolve issues w.r.t constraints, STA, Physical design, etc- Worked on generating Timing ECOs for various violations including setup, hold, trans etc- Custom Scripting in PT— Cell swapping for violations, Clock Network cell segregation, Skew analysis of paths etc. Synthesis- Executed and Owned Synthesis & Power Aware Synthesis with Fusion Compiler for all the blocks of an IP- Very well versed with Optimization techniques w.r.t Timing, Area and nuances related to QoR to achieve target PPA- Have impeccable knack of intricacies and understanding of Timing Paths to accomplish Timing Closure- Very well versed with Fusion Compiler shell in custom scripting, analysis and debug of various violations- Owned Full chip-level Synthesis & Physical Synthesis which include UPF, MBIST, SCAN Insertion- Familiar with execution of Top-Down (Flat) & Bottom-Up (Hierarchical) and handling various optimization strategies for better QoR- Familiar with writing Functional netlist ECOs based on the bugs identified in RTL. Constraints- Owned Constraints, well versed with defining Clocks, inter-clock relations etc. according to the clock tree structure- Handled Exceptions and IO budgeting for resolving numerous categories of violations for Timing Signoff- Familiar with GCA for checking constraints consistency with design and fixing corresponding errors/warnings. Formal Equivalence- Handled Formality for RTL2Gates, Gates2Gates including UPF, familiar with debugging Failing and Abort points. Power- Familiar with Power and its related activities such as PTPX, power calculation and debug etc. Vclp & Conformal Equivalence- Familiar with Synopsys VCLP & Cadence Low-Power (CLP-Verify) for checking UPF consistency with RTL and Netlist- Performed low power equivalence check (LP-EC) for RTL2gates and gates2gates including UPF- Familiar with generating Functional ECOs using Conformal ECO to be used in PnR implementation.Tools: Prime Time (PT), Design Compiler, Fusion Compiler, Formality, Conformal (Low Power Equivalence, ECO), ICC2, VCLP*, GCAOthers: Perforce, Git, Vim, Linux

Experience

1. Senior Lead Engineer

   高通

   May 2025 — Present · Hyderabad, IN

Education

• Indian Institute of Technology, Kanpur

  Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering

  2014 — 2018