Saisrikanth Eswaroju
IP Design Verification Engineer | RTL-to-GDSII Verification • Directed/Random Testing & Debug • MBA Candidate @ Haas
- Role
- Ip Design Verification Engineer at Cirrus Logic
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Saisrikanth Eswaroju
I’m an IP Design Verification Engineer with 7+ years in chip-level RTL-to-GDSII…
Experience
Ip Design Verification Engineer
May 2023 — Present · Austin, TX, US
Education
Portland State University
Master's degree
2012 — 2014
Jawaharlal Nehru Technological University
Bachelor of Technology (B.Tech.)
2007 — 2011
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