Sai Sreekanth Thallam
Digital design Verification Engineer @Cadence Design Systems
- Role
- Design Verification - 1 at Cadence
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Sai Sreekanth Thallam
VLSI Verification Engineer with 3.9 years of hands-on experience in memory subsystem…
Experience
Design Verification - 1
Jan 2023 — Present · Bangalore, IN
Education
St.Francis De Sales High School
High School
Government Institute Of Electronics - GIOE
Diploma of Education, ECE- Specilization in Embedded Systems
J.B.Institute of Engineering & Technology
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
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