V M Sai Prem Tammana

About V M Sai Prem Tammana

As a EDA CADEngineer at META Inc, I collaborate with the Silicon Products team at META Inc, our client, to develop and optimize semiconductor design flows. I have a Bachelor of Technology in Mechanical Engineering from Jain University, Bangalore, and I am currently pursuing a Master of Engineering in VLSI from Dayalbagh Educational Institute. My core competencies include Python, Bash, and TCL scripting, verification, Debugging.

Experience

1. Silicon Cad Engineer

   Meta

   Feb 2025 — Present · Bengaluru, IN

   Supported and maintained comprehensive scripts to automate the creation of register maps for ASIC and FPGA designs,transforming human-readable specs into RTL, C/Python modules, IP-XACT, and documentation.• Developed and maintained utilities for automatic generation of EDA tool file lists for simulation, synthesis, and verification.• Maintained and improved tools for generating memory wrapper modules and related design collateral for ASIC/FPGA systems.• Built and extended a Python-based framework to generate and manipulate Verilog/System Verilog using templating and designautomation.• Created a TCL script to map scan chain report errors to instance names for visual debugging in Star Vision Pro GUI.

Education

• Future Kids Global School Rjy

  High School

  2008 — 2015

• Dayalbagh Educational Institute

  diploma in mechanical engineering, Mechanical Engineering

  2015 — 2018

• Jain (Deemed-to-be University)

  Bachelor of Technology - BTech

  2018 — 2021