Sainarayanan K S
Director CAD - Central Engineering Methodology at Marvell Semiconductor
- Role
- Director Cad Flow & Methodology at Marvell Technology
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sainarayanan K S
18+years of experience in Physical Design from netist till GDS (including synthesis) & Timing, power & IR signoff, technology CAD- Experience in implementation of high performance ARM cores and Mali-GPU (G5X & G7X) series- Managing a team to implement high performance ARM cores and perform PPA analysis- Expanded the role to drive the high performance hard core hardening & achieving silicon success - Technical Mentorship- Full Chip Clock Tree Implementation and Sign-off- Technology worked include 130nm,90nm,65nm,45nm,28,16 & 7nm- Technical breadth ranging from standard cell characterization, SPICE simulation, Synthesis, Place & Route, Constraint management, Timing, Power & IR closure, deciding or coming up with signoff guidelines etc- Published around 20 International Papers in various VLSI conferences including DAC\'19,VLSID\'14, ISQED\'08, ISVLSI\'07, GLSVLSI\'07, ISCAS etc
Experience
Director Cad Flow & Methodology
Apr 2023 — Present · IN
Education
International Institute of Information Technology Hyderabad (IIITH)
MS (by Research), Low Power VLSI
2004 — 2007
University of Madras
B.E, Electronics and Communication
2000 — 2004
Skills
- Cmos
- Application-Specific Integrated Circuits (Asic)
- Asic
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