Sailaxmi Anumula

Experience

1. Rtl Design and Verification Engineer

   Sswitch Technologies

   Jun 2024 — Present · Hyderabad, IN

   Project: APB Protocol Verification (UVM)Developed an end-to-end UVM testbench including driver, sequencer, monitor, scoreboard, and environment.Verified read/write operations, error responses, and corner cases.Achieved 100% functional coverage using System Verilog randomization and covergroups.Project: AHB Protocol Verification (UVM with Pipelining)Built reusable and modular UVM components for pipelined AHB transfer scenarios.Verified burst, single, and error transfer types.Focused on pipelined address and data phase overlap, and arbitration behavior.Used Wave Drom for transfer diagram verification.Project: AXI3 Protocol VerificationVerified out-of-order, interleaved, and multi-ID transactions.Developed testbench with channel-specific components for AW, W, B, AR, and R.Covered exclusive access, write interleaving, and outstanding transactions.Integrated assertions and functional/code coverage using Synopsys VCS.Project: FIFO Design and VerificationDesigned and verified synchronous and asynchronous FIFOs in Verilog and System Verilog.Focused on full/empty flag behavior, overflow, and metastability handling.Built a self-checking testbench with scoreboard for data verification.

Education

• Government Institute of electronics

  Diploma , Industrial Electronics

  2017 — 2021

• Kakathiya University College of engineering and technology

  Bachelor of Technology - BTech, Electronics and communication engineering