Saikumar Koneti
Design verification engineer ll Gate 2020 and 2022 qualified
- Role
- Design Verification Engineer at AIonSi
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Saikumar Koneti
seeking opportunities where i can leverage my skills and knowledge to create innovative solutions.\" Technical skills:HDL:verilog programming including code coverageHVL:system verilog(SV) TB methodology: Universal verification methodology (UVM)shell scriptingGood knowledge on TCL,Python.Protocols: knowledge on bus protocol Apb,AHB,AxiGood understanding of PCIe transaction layer and LTSSM in physical layerDesigned I2c slave and UART with out fifo simulators and debuggers: synopsys verdi,vcs,questasim.Developed Makefile for Questasim tool.
Experience
Design Verification Engineer
Sep 2021 — Present
Education
Jyothimasthi institute of technology and science
Bachelor of Technology - BTech, Electronics and communication engineering
2015 — 2019
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