Sai Krishna

About Sai Krishna

With over 10 years of experience in the Physical Design domain, I have worked extensively across advanced technology nodes including 18A (1.8nm), 20A (2nm), 2nm, 5nm, N3, 7nm (TSMC), 10nm (Samsung), and 14nm (GlobalFoundries).Core Responsibilities- Place & Route (Block-level and Full-Chip): Floorplanning, macro placement, power planning, placement, CTS, routing - Project Setup & Sign-off: Parasitic extraction, STA, DRC, LVS, Antenna checks - Verification & Analysis- EMIR (Electro-Migration & IR drop analysis)- FEV (Formal Equivalence Verification)- PV (Physical Verification)- Timing Closure: ECO implementation for setup and hold violations - Issue Resolution: DRC/LVS/Antenna fixes, base-fill and metal-fill corrections CAD & Tool Flow Expertise- Strong exposure to Intel CAD flows for advanced technology nodes - Proficient with Cadence tools (Innovus, Tempus, Voltus, Virtuoso, Encounter) for synthesis-to-signoff - Skilled in Synopsys tools (Design Compiler, PrimeTime, ICC2, StarRC) and Mentor/Siemens EDA (Calibre for DRC/LVS/PEX)- End-to-end Synthesis → Floorplanning → Place & Route → STA → Sign-off flow execution - Developed and deployed 20+ CAD features to enhance automation, improve flow efficiency, and reduce turnaround time - Expertise in automation scripting with Tcl, Perl, and Shell for CAD flow integration and optimization Technical Skills- Multi-power domain design, power-gating architectures - Expertise in timing closure, EMIR analysis, CAD automation, and feature development - Hands-on with chip-level and chiplet-level integration flows

Experience

1. Sr Physical Design Engineer

   Intel

   Jul 2021 — Present · IN

Education

• Birla Institute of Technology and Science Pilani

  Bachelor of Technology, Electrical and Electronics Engineering