Sai Kiran Movva

WORK HISTORY

EDUCATION

SKILLS

ABOUT SAI KIRAN MOVVA

Self-Driven & Result Oriented professional with 9+ Years Hands-on Experience in the Digital to Sign Off Cycle Current work involves implementation and ECO of Cache Design Blocks in Intel’s Xeon Servers Working on deep sub-micron nodes (3,4,5 nm) Ownership of multiple Cache blocks in Server SoC Proficient with fusion compiler & all FC flows for block/sub-system level Developing scalable custom route solutions which can be reused independent of tool/flow/tech nodeCore Competencies Hands-on Experience working on Complex SoCs at Various Advanced Nodes Proficient in design debug techniques covering logical and physical synthesis, low power methodology, place and route, custom route/push downs, Timing budgeting & ECO Methodologies Well versed in both Cadence & Synopsys EDA toolsOver the Years Achievements Hands on work experience in all phases of RTL to GDSII which includes syn, PnR, fev, ptpx, timing, pv, caliber & ECO. ECO’ d a 15K gate conformal ECO-based patch into production along with parallel ECO of multiple blocks in the sub-system Path finding & clearing floorplan size reductions for implementing bigger cache blocks at advanced nodes Owned timing analysis for sign-off on complex latch-based design for tape out (Design size > 5M) Multiple successful tape outs at various nodes working on different aspects of the flow.