Saigoutham Sunkara
Hardware Engineering Technical Leader | Acacia @ Cisco | USC | 224 & 448 Gbps Transceivers
- Role
- Hardware Engineering Technical Leader at Cisco
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Saigoutham Sunkara
A passionate Analog circuit designer with industrial experience in state of the art I/O design.Lab Equipment: High Frequency Oscilloscopes, Network Analyzer, Spectrum Analyzer, Multimeter, JBERTProcess nodes: 10nm, 14nm FinFet, 40nm & 130nmLanguages: Verilog, VHDL, C, C++, PERLDigital DesignMOS Delay models, Logical Effort, Latches and Flip-flops, Clocking schemes, Timing analyses, Power, MOS Device physics, PVT VariationsAnalog Layout DesignMonte Carlo Analysis, PVT Variations, ESDs, BondPads, RC Extraction, Antenna Rules, Pattern Denstiy Rules,Inductor parasitic model, IR Voltage drop Analog IC Design Second order system analysis, Wideband feedback Amplifiers, Bandgap References, Basic OPAMP Design, Two-stage OPAMP design and Frequency compensation, Fully Differential operation, Common Mode FeedbackRadio Frequency IC Design Noise, Nonlinearity, Basic communication theory, Complex signal processing, Transmitter and Receiver Architectures, LNA Design, Active and Passive Mixer Fundamentals, Oscillator basics, PLLsData ConvertersSampling, DAC Architectures, ADC principles, SAR ADC design, Delta-sigmasRadio Active Filter designActive inductance realization, Nth order filters, Delay equalizers, Butterworth Filter, Chebyshev FilterEDA tools: Cadence Virtuoso, Hspice, Assura, ModelSim, Calibre, HSpice, Eagle, Matlab, Xilinx, Simulink
Experience
Hardware Engineering Technical Leader
May 2024 — Present · San Jose, CA, US
Working on 448Gbps, 224Gbps & 112Gbps SERDES/Transceivers for High-Speed optical interfaces in 2nm/3nm/4nm nodesDesigned Analog Front End variants (TERM/ CTLE/ VGA/-ve Charge pump) & BGR collaborating with other designers to converge on architecture, performance targets, and implementation details
Education
National Institute of Technology Warangal
Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering
2009 — 2013
University of Southern California
Master's degree, Electrical and Electronics Engineering
2013 — 2015
Skills
- C++
- C
- Pll
- Verilog
- Pspice
- Mixed Signal
- Analog Circuit Design
- Vhdl
- Sensors
- Cadence Virtuoso
- Analog
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