Shabbir Saifee
Lead Silicon Design Engineer at Google
- Role
- Lead Silicon Design Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Shabbir Saifee
Currently working as Lead STA Engineer at Google, Bangalore.Skilled in fullchip timing closure, Logic Synthesis, Place & Route, CTS, Floor-planning, Timing, ECOs, clocking strategies and constraints development, Layout and DRC, IR drop analysis.
Experience
Lead Silicon Design Engineer
Aug 2023 — Present · Bengaluru, IN
Education
NIRMA university
Master of Technology (MTech), VLSI Design
2012 — 2014
V.V.P. Engineering college,rajkot
Bachelor of Engineering (BE), Electrical, Electronics and Communications Engineering
2007 — 2011
Skills
- Perl
- Vhdl
- Verilog
- Pspice
- Matlab
- C
- Xilinx
- Synopsys Primetime
- Synopsys Ic Compiler
- Modelsim
- Vlsi
- Tcl-Tk
- Pyxis
- Static Timing Analysis
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