Saif Abrar

About Saif Abrar

Learning continuously. Innovating daily. Leading to delight and grow.Contributing to the org at multiple levels – strategic planning to innovation pipeline, hands-on development to team leadership, working with senior execs to cross-functional global teams and customers, project planning & management, hiring, mentoring, patents filing, academic collaborations (17) and conf presentations (37).Hands-on IC and leadership in global projects for SW stacks and HW infrastructure simulation models of embedded to enterprise HPC and AI systems. Experienced in architecture, performance and power explorations, early software bringup, pre-Si verification and reliability testing using system-level simulation.Unique blend of professional experiences and expertise in- Strategic planning: Next projects to academic collaborations- Interactions: Global executives to external customer- Leadership: Communication to consensus- Systems: Embedded to supercomputing- Design: System-level to microarchitecture- Collaborations: Academics to open-source- Innovations: Patents, publications, posters, hackathons- Programming: Assembly to HLL’s to scripting- Exploration: Architecture, performance, power- Simulation: RTL, C++, QEMU, SystemC- Modeling: Cycle-accurate, approximate, functional, TLM- IBM Academic AmbassadorEmbedded, DSP, graphics, HPC expertise in- USA DoE SUMMIT supercomputer- IBM POWER HPC systems- Intel mobile comm platforms- Philips TriMedia & R.E.A.L. DSP- Arm cores and systemsExperienced in system-level simulation, for- Functional, approximate and cycle-accurate modeling- Performance analysis & optimizations- Software bring-up and debug- RTL pre-Si verification- Power dissipationPerformance analysis and optimizations using- Traffic gen, perf counters, sim for cache, pipeline, etc- Benchmarks like Dhry/Whet-stone, SPEC, EEMBC, etc- Enterprise workloads like OS, SAP, etc- Valgrind, gprof, perf, etc.Innovative methodologies and tools implemented, such as- Perf counters in IBM Power simulator- Power dissipation and visualization tool for Arm core- Energy model for Philips R.E.A.L. DSP- Dual-mode (Python/TCL) scripting- Hw/Sw co-verification tool for system sim- Application model of MPEG-1 Layer-3 softwareFiled patents related to- TCL-to-assembly flow- High-level modeling- IdentificationInterests:Team leadership, innovations, open source, new technologies, system-level HW/SW, embedded to HPC systems, simulation, analysis and optimizations, hiring, mentoring.

Experience

1. Advisory Systems Engineer

   IBM

   Jan 2012 — Present · Bangalore, IN

   Technical leadership, hands-on contributions and breakthrough innovations in research, architecture, development and analysis of system/CPU models, tools and FW for IBM POWER cores and systems. Hands-on dev/debug experience with C++, TCL, Python, assembly, SystemC, Simics, QEMU, etc. Performance analysis, SW bringup, team hiring, academic relations, conference presentations, mentoring juniors and students.

Education

• Aligarh Public School

  10, High-school

  1982 — 1992

• Aligarh Muslim University

  B.Tech., Computer Engg.

  1994 — 1998

• Indian Institute of Technology, Delhi

  M.Tech., VLSI Design, Tools and Technology (VDTT)

  1998 — 2000

• Aligarh Muslim University

  10+2, Physics, Chemistry, Mathematics

  1992 — 1994

• TalTech – Tallinn University of Technology

  Doctor of Philosophy (PhD), Department of Computer Engineering

  2011 — 2016

Skills

• Shell Scripting
• Gnu Tools
• Software Engineering
• Systemc
• Computer Architecture
• Arm
• Algorithms
• Wireless
• Digital Signal Processors
• Software Development
• Unix
• Rtos
• System Design
• Architectures
• Soc
• Dsp
• C
• Vlsi
• Embedded Software
• Integration
• C++
• Simulations
• Linux
• Semiconductors
• Software Design
• Architecture
• Device Drivers
• Tcl
• Perl
• Embedded Systems
• Eda
• Debugging
• System Architecture
• Arm Architecture