Saidesh Kumar Pasupuleti
SoC Design Engineer at Intel | Ex-LeadSoc
- Role
- Soc Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Saidesh Kumar Pasupuleti
Skilled in low-power design, timing closure, physical verification, EM & IR closure. Main domain of working is Physical design. Experienced in Full-chip implementation, PAD/BUMP placement and RDL routing. Hands on experience on Industry tools such as DC, ICC/ICC2, ICV, PRIMETIME, CALIBRE, REDHAWK, INNOVUS, TEMPUS, GENUS and FORMALITYHands on experience on lower tech nodes like 14nm, 10nm, 8nm, 7nm, 5nm, 4nm and 3nmLeading High speed serdes test chips and implementation, Successfully taped out 3 test chips in 10nm and 8nm FINFET NodesSuccessfully taped out 9 test chips over the span of 3 years
Experience
Soc Design Engineer
Jul 2023 — Present · Bengaluru, IN
Education
Anna University Chennai
Master of Engineering - MEng, Applied Electronics
CVR College of Engineering, Hyderabad
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
Skills
- Asic
- Electronics
- Matlab
- Asic Design
- Analog Layout Design
- Microprocessors
- Full Custom Design Flow
- Verilog
- Mixed-Signal Ic Design
- Embedded C
- Tcl Scripting
- Microcontrollers
- C
- Physical Design
- Tcl
- Analog Circuit Design
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.